Csse4010

’’’ signal Inputs : std_logic_vector(3 downto 0) := “0000”; signal OutputF : std_logic;

begin

test_logic : Prac1PrimeNumFunciton port map ( A => Inputs(3), B => Inputs(2), C => Inputs(1), D => Inputs(0), F => OutputF );

test: process begin

for i in 0 to 15 loop wait for 20ns;

if (Inputs = "0010" or Inputs = "0011" or Inputs = "0101" or Inputs = "0111" or Inputs = "1011" or Inputs = "1101") then
    assert (OutputF = '0') report "Faulty Logic!" severity error;
else
    assert (OutputF = '1') report "Faulty Logic!" severity error;
end if;
 
-- Remember to add the following up the top: use ieee.std_logic_unsigned.all;
Inputs <= Inputs + '1'; end loop; wait; end process; '''